XRT4500 Datasheet, PDF (61/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
áç
nal to the “SCTE_IN” input pin of the DCE SCC.
There is no need to design in extra glue logic to multi-
plex the “SCTE” output pin of the XRT4500 with the
TXC output pin of the DCE SCC.
Additionally, if the DCE Equipment is being interfaced
to a DTE Terminal which does not support the SCTE
signal, (e.g., the XRT4500 is now operating in the “2-
Clock” Mode), and if the “DCE/DTE Interface” config-
uration settings are such that the “TXD-to-TXC” set-
up time requirements of the DCE SCC are being vio-
lated, then the user can eliminate this problem by in-
voking the “Clock Invert” feature of the XRT4500.
1.3.7 The Latch Mode of Operation
The Latch Mode of operation permits the user to latch
the state of the “Mode Control” input pins (M[2:0]) into
the XRT4500 internal circuitry. This feature frees up
of the signals, driving the M[2:0] input pins (pins 6, 5,
and 4) for other purposes.
Because of this feature, it is permissible to control the
state of the “M[2:0]” input pins via certain signals
within a bi-directional data bus (which is controlled by
a microprocessor or microcontroller).
The user invokes this feature by driving the “LATCH”
input pin (pin 44) from “low” to “high”. During this
“low” to “high” transition, the contents of the “M[2:0]”
input pins will be “locked” (or latched) into internal cir-
cuitry within the XRT4500. At this point (as long as
the “LATCH” input pin remains “high”) the user's sys-
tem can do other things with the signal which are also
driving the “M[2:0]” without affecting the behavior the
XRT4500.
The user disables the “LATCH” feature by driving the
“LATCH” input pin, from “high” to “low”. Once the
“LATCH” input pin is “low”, then the behavior of the
XRT4500 will be dictated by the state of the “M[2:0]”
input pins.
1.3.8 The Registered Mode of Operation
The XRT4500 includes a feature which is known as
“Registered Mode” operation. The user can enable
the “Registered” Mode by setting the “REG” input pin
“HIGH”. Conversely, the user can disable the “Regis-
tered” Mode by setting the “REG” input pin “LOW”.
If the user enables the “Registered” Mode, then the
following things will happen.
a. The XRT4500 will be configured to sample and
latch the contents of the “TX5D” and “TX8D” input
pins, upon the rising edge of the “REG_CLK” input
signal.
b. The XRT4500 will be configured to output data (to
the SCC) via the “RX5D” and “RX8D” output pins, up-
on the rising edge of the “REG_CLK” signal.
This feature is useful in application, which use a SCC
or a Microcontroller (that requires an external clock
signal to sample the “DSR” and the “RI” (or “TM”) sig-
nals. Further, this feature also configures the
XRT4500 to sample the state of the “DTR” and the
“RL” signal upon the rising edge of an external clock
signal.
If the user invokes this feature, then the relationship
between the XRT4500 and the SCC/Microprocessor
is as depicted below in Figure 31.
FIGURE 31. AN ILLUSTRATION OF THE EFFECTIVE INTERFACE BETWEEN THE XRT4500 AND THE SCC/MICROPRO-
CESSOR WHEN THE “REGISTERED” MODE IS ENABLED
XRT4500
TX5D
RX5D
TX8D
RX8D
REG_CLK
DTR_Signal
DSR_Signal
RL_Signal
RI_Signal
External Clock
µC/µP
58