XRT4500 Datasheet, PDF (49/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
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The DTE Terminal
The DTE Terminal is responsible for sourcing/gener-
ating all of the following signals.
• TXD - Transmit Data
• TXCE (or SCTE) - Transmit Clock Echo
• DTR - Data Terminal Ready
• RTS - Request to Send
• LL - Local Loop-back Indicator
• RL - Remote Loop-back Indicator
Further, the DTE Terminal is responsible for receiv-
ing/terminating all of the following signals.
• RXD - Receive Data
• TXC - Transmit Clock
• RXC - Receive Clock
• DSR - Data Set Ready
• DCD - Data Carrier Detect
• CTS - Clear-to-Send
• RI (Ring Indicator)
• TM (Test Mode Indicator).
Because of this, whenever the XRT4500 is configured
to operate in the “DTE” Mode, then the following con-
figuration conditions are “TRUE”.
• Two “high-speed” Transmitters are enabled, and
• Three “high-speed” Receivers are enabled.
• Four “low-speed” Transmitters are enabled, and
• Four “low-speed” Receivers are enabled.
Other Comments about DCE and DTE Equipment
Whenever DCE and DTE Equipment are interfaced to
each other, the DCE Equipment is typically the
source of all timing signals. The DTE Equipment will
typically function as a “Clock Slave”.
1.3.3 The LP - Loop-Back Enable/Disable
Select Pin
As mentioned earlier, the XRT4500 can be configured
to operate in the loop-back mode. Setting the “LP” in-
put pin “high” disables the loop-back mode (within the
XRT4500). Conversely, setting this input “low” config-
ures the XRT4500 to operate in the “TXD/RXD” loop-
back mode.
A detailed description of the “TXD/RXD” loop-back
Mode is presented below.
Behavior of DTE/DCE Mode Devices, when the
Loop-Back Mode is Disabled
Figure 17 presents an illustration of a DTE and DCE
Terminal interfaced to each other when no XRT4500
Loop-Back Mode has een configured.
FIGURE 17. ILLUSTRATION OF BOTH THE DTE AND DCE MODE XRT4500 OPERATING, WHEN THE LOOP-BACK
MODE IS DISABLED
SCC (L)
TXD
SCTE
DTE (#1)*
60
TX1
63
TXD
78
62
79
67
TX2
64
SCTE
77
65
76
DTE (#2)
RX1
1
74
RX2
SCC (R)
TXD_IN
SCTE_IN
TXC_IN
RXC_IN
RXD_IN
70
TXC
70
73
RX3
71
71
TX3
68
TXC
77
RXC
64
74
RX2
76
65
TX2
67
RXC
78
RXD
63
1
RX1
79
60
62
TX1
RXD
XRT4500
XRT4500 * Indicates scenario # from Table 8
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