XRT4500 Datasheet, PDF (63/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
áç
FIGURE 33. ILLUSTRATION OF THE INTERNAL OSCILLATORS WITHIN THE XRT4500
SCC (L)
TXD
DTE
TX1
TXD
SCTE
SCTE
TX2
TXC_IN
RXC_IN
RXD_IN
73
OOSSCC R X 3
74
OOSSCC R X 2
RX1
XRT4500
TXC
RXC
RXD
If the user enables the Internal Oscillator, within the
XRT4500, then the XRT4500 will output between a
32kHz and a 64kHz clock signal via the RX2D and
RX3D signals. When the XRT4500 is interfaced to the
DTE SCC, this translates into the XRT4500 generating
the timing signals for “TXC” and the “RXC” input signals.
As a consequence, the DTE SCC is provided with all of
the requisite timing signals that it would normally have, if
it were interfaced to a DCE Terminal. This feature per-
mits the user to implement a wide variety of diagnostic
programs for DTE Equipment stand-alone testing.
NOTE: The Internal Oscillator feature is only available if the
XRT4500 has been configured to operate in the DTE Mode.
1.3.10 Glitch Filters
Occasional extraneous glitches on control/handshake
signal inputs such as CTS, RTS, DTR and DSR can
have damaging effects on the integrity of a connection.
The XRT4500 is equipped with lowpass filters on the
input of each of the receivers for the control and
handshake signals. These filters eliminate glitches
which are narrower than 10µs. The user may disable
these filters by setting EN_FLTR to logic 0.
1.3.11 Data Inversion
Similar to TXC, there is a provision in the XRT4500 to
invert the TXD and RXD signals. Once the Setting
the DTINV* input to logic 0 enables an inverter at the
output of RX1 and input of TX1.
1.3.12 Data Interlude
Similar to TXC, there is a provision in the XRT4500 to
invert the TXD and RXD signals. Once the Setting the
DTINV* input to logic 0 enables an inverter at the out-
put of RX1 and input of TX1.
2.0 RECEIVER AND TRANSMITTER
SPECIFICATIONS
Table 3 and Table 4, which are for the XRT4500 re-
ceiver and transmitter sections respectively, summa-
rize the electrical requirements for V.35, V.11, V.10,
and RS232 interfaces. These tables provide virtually
all of the electrical information necessary to describe
these 4 interfaces in a concise form.
3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL
TIME CONTROL
SLEW_CNTL (pin 47) is an analog output that con-
trols transmitter pulse rise and fall time for the V.10
and V.28 modes. Connecting a resistor, RSLEW, hav-
ing a value between 0 and 200 kΩ from this pin to
ground controls the rise/fall times for V.10 and the
slew rate for V.28 as shown in Figure 34 and
Figure 35 respectively.
60