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XRT4500 Datasheet, PDF (21/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC | |||
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
áç
PIN Signal
#
53 OSCEN
DTE
MODE
DCE
MODE
TYPE FUNCTION
I Test Oscillator Enable â Active Low;
This active-low input pin permits the user to enable or disable the
âInternal Oscillatorâ within the XRT4500. If the user enables this fea-
ture then the XRT4500 will begin generating a clock signal via both
the RX2D and RX3D output pins. The frequency of this clock signal
ranges between 32kHz and 64kHz.
This clock signal can be used to support âStand-Alone DTE Diag-
nosticâ Testing.
Setting this input to â0â enables the âInternal Oscillatorâ.
Setting this input to â1â disables the âInternal Oscillatorâ.
Note: The âInternal Oscillatorâ is only available if the XRT4500 is
operating in the DTE Mode.
If LP = â0â The Clock Signal (32 - 64kHz) is available on Rx3D.
If LP = â0â and EC = â0â the clock signal is available on RX2D.
54 CLKINV
NOTE: This input pin contains an internal 20k⦠pull-up to VDD.
I Invert Clock Input Pin â This âActive -Lowâ input pin permits the
user to either enable or disable the âClock/Inversionâ feature. The
exact manifestation of the âClock Inversionâ feature depends upon
whether the XRT4500 is operating in the âDCEâ or âDTEâ Mode.
If the XRT4500 is operating in the DTE Mode, then the RX3D output
signal (which is receiving the TXC signal) will be inverted before it is
outputted to the terminal equipment.
If the XRT4500 is operating in the DCE Mode, then the TX3D input
signal (which is transmitting the TXC signal) will be inverted before it
converted into the analog format and is output to the line.
Setting this input pin âLowâ enables the âClock Inversionâ feature.
Conversely, setting this input pin âHighâ disables this feature.
55 DTINV
56 VSS_T123
57
GND
58 VDD_T123
59 GND_T12
NOTE: This input pin contains an internal 20k⦠pull-up to VDD.
I Invert Data â Active Low; Logic 0: Data Inverted.
Logic 1: Data not Inverted. Internal 20K⦠pull-up VDD.
-6V Power Supply Signal: This supply voltage is internally gener-
ated by the Switching Regulator Circuit within the XRT4500.
Digital Ground: for transmitters 1, 2, and 3
Analog VDD: for transmitters 1, 2, and 3
Analog Ground: Transmitters 1 and 2
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