XRT83L30_06 Datasheet, PDF (58/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION
REGISTER ADDRESS
00110
BIT #
NAME
FUNCTION
REGISTER RESET
TYPE VALUE
D7
Reserved
RUR
0
D6
DMOIS Driver Monitor Output Interrupt Status: This bit is set to a "1" RUR
0
every time when DMO status has changed since last read.
D5
FLSIS FIFO Limit Interrupt Status: This bit is set to a "1" every time
RUR
0
when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status
has changed since last read.
D4
LCVIS Line Code Violation Interrupt Status: This bit is set to a "1"
RUR
0
every time when LCV status has changed since last read.
D3
NLCDIS Network Loop-Code Detection Interrupt Status: This bit is set RUR
0
to a "1" every time when NLCD status has changed since last
read.
D2
AISDIS AIS Detection Interrupt Status: This bit is set to a "1" every
RUR
0
time when AISD status has changed since last read.
D1
RLOSIS Receive Loss of Signal Interrupt Status: This bit is set to a "1" RUR
0
every time RLOS status has changed since last read.
D0
QRPDIS Quasi-Random Pattern Detection Interrupt Status: This bit is RUR
0
set to a "1" every time when QRPD status has changed since
last read.
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