XRT83L30_06 Datasheet, PDF(57/78 Page) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30_06 Datasheet, PDF (57/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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REV. 1.0.1

XRT83L30

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION

NLCD Network Loop-Code Detection:

This bit operates differently in the Manual or the Automatic Net-

work Loop-Code detection modes.

In the Manual Loop-Code detection mode (NLCDE1 =â0â and

NLCDE0 =â1â, or NLCDE1 =â1â and NLCDE0 =â0â) this bit gets

set to â1â as soon as the Loop-Up (â00001â) or Loop-Down

(â001â) code is detected in the receive data for longer than 5 sec-

onds. The NLCD bit stays in the â1â state for as long as the chip

detects the presence of the Loop-Code in the receive data and it

is reset to â0â as soon as it stops receiving it. In this mode if the

NLCD interrupt is enabled the chip will initiate an interrupt on

every transition of the NLCD.

When the Automatic Loop-Code detection mode (NLCDE1 =â1â

and NLCDE0 =â1â) is initiated, the state of the NLCD interface bit

is reset to â0â and the chip is programmed to monitor the receive

input data for the Loop-Up Code. This bit is set to a â1â to indicate

that the Network Loop Code is detected for more than 5 sec-

onds. Simultaneously the Remote Loop-Back condition is auto-

matically activated and the chip is programmed to monitor the

receive data for the Network Loop-Down Code. The NLCD bit

stays in the â1â state for as long as the Remote Loop-Back condi-

tion is in effect even if the chip stops receiving the Loop-Up

Code. Remote Loop-Back is removed if the chip detects the

â001â pattern for longer than 5 seconds in the receive data.

Detecting the â001â pattern also results in resetting the NLCD

interface bit and initiating an interrupt provided the NLCD inter-

rupt enable bit it active. When programmed in the Automatic

detection mode, the NLCD interface bit stays âHighâ for the entire

time the Remote Loop-Back is active and initiates an interrupt

anytime the status of the NLCD bit changes. In this mode the

host can monitor the state of the NLCD bit to determine if the

Remote Loop-Back is activated.

AISD Alarm Indication Signal Detect: This bit is set to a "1" to indi-

cate All Ones Signal is detected by the receiver. The value of this

bit is based on the current status of Alarm Indication Signal

detector. If the AISDIE bit is enabled, any transition on this bit will

generate an Interrupt.

RLOS Receive Loss of Signal: This bit is set to a "1" to indicate that

the receive input signal is lost. The value of this bit is based on

the current status of the receive input signal. If the RLOSIE bit is

enabled, any transition on this bit will generate an Interrupt.

QRPD Quasi-random Pattern Detection: This bit is set to a "1" to indi- RO

cate the receiver is currently in synchronization with QRSS pat-

tern. The value of this bit is based on the current status of Quasi-

random pattern detector of. If the QRPDIE bit is enabled, any

transition on this bit will generate an Interrupt.

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