XRT83L30_06 Datasheet, PDF (16/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
CONTROL FUNCTION
RESET
41
SR/DR
28
LOOP1
29
LOOP0
30
EQC4
21
SDI
EQC3
22
SDO
EQC2
23
SCLK
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Hardware Reset (Active "Low")
When this pin is tied “Low” for more than 10µs, the device is put in the reset
state.
Pulling RESET “Low” while the ICT pin is also “Low” will put the chip in fac-
tory test mode. This condition should never happen during normal operation.
NOTE: Internally pulled “High” with a 50kΩ resistor.
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Single-Rail/Dual-Rail Data Format
In Hardware mode, connect this pin "Low" to select transmit and receive
data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and
decoder are not available.
Connect this pin "High" to select single-rail data format.
NOTE: Internally pulled "Low" with a 50kΩ resistor.
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Loop-back Control pin 1
Loop-back Control pin 0
In Hardware mode, LOOP[1:0] pins are used to control the Loop-back func-
tions according to the following table:
LOOP1
0
0
1
1
LOOP0
MODE
0
Normal Mode
1
Local Loop-Back
0
Remote Loop-Bac
1
Digital Loop-Back
NOTE: Internally pulled "Low" with a 50kΩ resistor.
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Equalizer Control Input pin 4
In Hardware mode, this pin together with EQC[3:0] are used for controlling
the transmit pulse shaping, transmit line build-out (LBO), receive monitoring
and also to select T1, E1 or J1 modes of operation. See Table 5 for descrip-
tion of Transmit Equalizer Control bits.
Serial Data Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
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Equalizer Control Input pin 3
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Data Output
O Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
I
Equalizer Control Input pin 2
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Interface Clock Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
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