XRT83L30_06 Datasheet, PDF (17/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
CONTROL FUNCTION
EQC1
CS
24
I
Equalizer Control Input pin 1
See EQC4/SDI description for further explanation for the usage of this pin.
Chip Select Input
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
EQC0
INT
25
I
Equalizer Control Input pin 0
See EQC4/SDI description for further explanation for the usage of this pin.
O Interrupt Output
Host mode, SEE”SERIAL INTERFACE” ON PAGE 5.
ALARM FUNCTION/OTHER
SIGNAL NAME
PIN #
ATAOS
27
ICT
59
TYPE
I
I
DESCRIPTION
Automatic Transmit “All Ones” Pattern
In Hardware mode, a "High" level on this pin enables the automatic trans-
mission of an "All Ones" AMI pattern from the transmitter when the receiver
has detected an LOS condition. A "Low" level on this pin disables this func-
tion.
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
In-Circuit Testing (active "Low")
When this pin is tied “Low”, all output pins are forced to a “High” impedance
state for in-circuit testing.
Pulling RESET “Low” while ICT pin is also “Low” will put the chip in factory
test mode. This condition should never happen during normal operation.
NOTE: Internally pulled “High” with a 50kΩ resistor.
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