XRT83L30_06 Datasheet, PDF (39/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
NLCDE[1:0] control the Loop-Code detection according to Table 13.
TABLE 13: LOOP-CODE DETECTION CONTROL
NLCDE1 NLCDE0
CONDITION
0
0 Disable Loop-Code Detection
0
1 Detect Loop-Up Code in Receive Data
1
0 Detect Loop-Down Code in Receive Data
1
1 Automatic Loop-Code detection and Remote Loop-Back Activation
Setting the Hardware pins or interface bits NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-
Up code in the receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer
than 5 seconds the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues
to receive the Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an
interrupt on every transition of NLCD. The host has the option to ignore the request from the remote terminal,
or to respond to the request and manually activate Remote Loop-Back. The host can subsequently activate the
detection of the Loop-Down Code by setting NLCDE1="1" and NLCDE0="0". In this case, receiving the "001"
Loop-Down Code for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled,
the chip will initiate an interrupt on every transition of NLCD. The host can respond to the request from the
remote terminal and remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and
NLCDE0="1") and Loop-Down (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD pin or
interface bit will be set to "1" upon receiving the corresponding code in excess of 5 seconds in the receive data.
In Host mode the chip will initiate an interrupt any time the status of the NLCD bit changes and the Network
Loop-code interrupt is enabled.
Setting the Hardware pins or interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code
detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to “110”. As this mode is
initiated, the state of the NLCD pin or interface bit is reset to "0" and the chip is programmed to monitor the
receive input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data
for longer than 5 seconds in addition to setting the NLCD pin or interface bit, Remote loop-back is
automatically activated. The chip stays in remote loop-back even if it stops receiving the "00001" pattern. After
the chip detects the Loop-Up code, sets the NLCD pin (bit) and enters Remote loop-back, it automatically
starts monitoring the receive data for the Loop-Down code. In this mode however, the NLCD pin (bit) stays set
even if the receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote loop-
back is still in effect. Remote loop-back is removed if the chip detects the "001" Loop-Down code for longer
than 5 seconds. Detecting the "001" code also results in resetting the NLCD pin (bit) and initiating an interrupt.
The Remote loop-back can also be removed by taking the chip out of the Automatic detection mode by
programming it to operate in a different state. The chip will not respond to remote loop-back request if an
Analog loop-back is activated locally. When programmed in Automatic detection mode the NLCD pin (bit) stays
"High" for the whole time the Remote loop-back is activated and in the Host mode it initiates an interrupt any
time the status of the NLCD bit changes provided the Network Loop-code interrupt is enabled.
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS)
The XRT83L30 includes a QRSS pattern generation and detection block for diagnostic purposes that can be
activated only in the Host mode by setting the interface bits TXTEST2=”1”, TXTEST1=”0” and TXTEST0=”0”.
For T1 systems, the QRSS pattern is a 2²⁰-1pseudo-random bit sequence (PRBS) with no more than 14
consecutive zeros. For E1 systems, the QRSS pattern is 2¹⁵ -1 PRBS with an inverted output. With QRSS and
Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD interface bit, all
main functional blocks within the transceiver can be verified.
When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD
changes from “Low” to “High”. After pattern synchronization, any bit error will cause QRPD to go “Low” for one
clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt.
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