XRT83L30_06 Datasheet, PDF (12/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
JITTER ATTENUATOR
SIGNAL NAME
PIN #
JABW
46
JASEL1
47
JASEL0
48
TYPE
I
I
DESCRIPTION
Jitter Attenuator Bandwidth
In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth
is 10Hz (normal mode). Setting JABW to “1” selects a 1.5Hz Bandwidth for
the Jitter Attenuator and the FIFO length will be automatically set to 64 bits.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz, and the
state of this pin has no effect on the Bandwidth. See table under JASEL1 pin,
below.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Jitter Attenuator select pin 1
Jitter Attenuator select pin 0
In Hardware mode, JASEL0, JASEL1 and JABW pins are used to place the
jitter attenuator in the transmit path, the receive path or to disable it and set
the jitter attenuator bandwidth and FIFO size per the following table.
JABW JASEL1 JASEL0 JA Path
0
0
0
Disabled
0
0
1
Transmit
0
1
0
Receive
0
1
1
Receive
1
0
0
Disabled
1
0
1
Transmit
1
1
0
Receive
1
1
1
Receive
JA BW (Hz)
T1
E1
------ ------
3
10
3
10
3
10
------ ------
3
1.5
3
1.5
3
1.5
FIFO Size
T1/E1
------
32/32
32/32
64/64
--------
32/64
32/64
64/64
NOTE: These pins are internally pulled "Low" with 50kΩ resistors.
CLOCK SYNTHESIZER
SIGNAL NAME
MCLKE1
PIN #
13
TYPE
I
DESCRIPTION
E1 Master Clock Input
This input signal is an independent 2.048MHz clock for E1 system with
required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.
MCLKE1 is used in the E1 mode. Its function is to provide internal timing for
the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,
reference clock during transmit all ones data and timing reference for the
microprocessor in Host mode operation.
MCLKE1 is also input to a programmable frequency synthesizer that under
the control of the CLKSEL[2:0] inputs can be used to generate a master
clock from an accurate external source. In systems that have only one mas-
ter clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation.
NOTES:
1. See pin descriptions for pins CLKSEL[2:0].
2. Internally pulled “Low” with a 50kΩ resistor.
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