XRT83L30_06 Datasheet, PDF (19/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
ALARM FUNCTION/OTHER
SIGNAL NAME
NLCD
AISD
QRPD
PIN #
38
39
40
TYPE
O
O
O
DESCRIPTION
Network Loop-Code Detection Output pin
This pin operates differently in the Manual or the Automatic Network Loop-
Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and NLCDE0 =”1”,
or NLCDE1 =”1” and NLCDE0 =”0”) this pin gets set to “1” as soon as the
Loop-Up (“00001”) or Loop-Down (“001”) code is detected in the receive data
for longer than 5 seconds. The NLCD pin stays in the “1” state for as long as
the chip detects the presence of the Loop-Code in the receive data and it is
reset to “0” as soon as it stops receiving it.
When the Automatic Loop-Code detection mode (NLCDE1 =”1” and
NLCDE0 =”1”) is initiated, the NLCD output pin is reset to “0” and the chip is
programmed to monitor the receive input data for the Loop-Up Code. The
NLCD pin is set to a “1” to indicate that the Network Loop Code is detected
for more than 5 seconds. Simultaneously the Remote Loop-Back condition is
automatically activated and the chip is programmed to monitor the receive
data for the Network Loop-Down Code. The NLCD pin stays in the “1” state
for as long as the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up Code. Remote Loop-Back is removed if the chip
detects the “001” pattern for longer than 5 seconds in the receive data.
Detecting the “001” pattern also results in resetting the NLCD output pin.
Alarm Indication Signal Detect Output pin
This pin is set to "1" to indicate that an All Ones Signal is detected by the
receiver. The value of this pin is based on the current status of Alarm Indica-
tion Signal detector.
Quasi-random Pattern Detection Output pin
This pin is set to "1" to indicate that the receiver is currently in synchroniza-
tion with the QRSS pattern. The value of this pin is based on the current sta-
tus of Quasi-random pattern detector.
POWER AND GROUND
SIGNAL NAME
PIN #
TAGND
7
TAVDD
9
RAGND
6
RAVDD
3
VDDPLL
12
GNDPLL
15
DVDD
36
AVDD
31
DGND
37
AGND
32
TYPE
****
****
****
****
****
****
****
****
****
****
DESCRIPTION
Transmitter Analog Ground
Transmitter Analog Positive Supply (3.3V + 5%)
Receiver Analog Ground
Receiver Analog Positive Supply (3.3V± 5%)
Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
Analog Ground for Master Clock Synthesizer PLL
Digital Positive Supply (3.3V± 5%)
Analog Positive Supply (3.3V± 5%)
Digital Ground
Analog Ground
16