XR17V352IB-0A-EVB Datasheet, PDF (55/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

REV. 1.0.4
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
TABLE 17: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
0
0
0
0
0
9
0
0
1
1
1
1
1
1
1
1
MSR[6]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MSR[5]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MSR[4]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DELAY IN DATA BIT(S) TIME
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSR [3]: Transmitter Disable
This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set
to a logic 1, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will
stay in the FIFO and will not be sent out. When this bit is set to a logic 0, the bytes currently in the TX FIFO will
be sent out. Please note that setting this bit to a logic 1 stops any character from going out. Also, this bit must
be a logic 0 for the Send Char Immediate function (see MCR[3]).
 Logic 0 = Enable Transmitter (default).
 Logic 1 = Disable Transmitter.
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