XR17V352IB-0A-EVB Datasheet, PDF (35/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

REV. 1.0.4
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
FIGURE 11. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART
UARTA
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
RXA
RTSA#
TXA
TXB
CTSB#
RXB
Remote UART
UARTB
Transmitter
Auto CTS
Monitor
Receiver FIFO
Trigger Reached
Auto CTS
Monitor
CTSA#
RTSB#
Auto RTS
Trigger Level
RTSA#
CTSB#
TXB
Assert RTS# to Begin
Transmission
1
ON
2
7
ON
3
OFF
8 ^OFF
10 ON
11
ON
Data Starts
4
6 _Suspend ^Restart
9
RXA FIFO
INTA
(RXA FIFO
Receive
Data
RX FIFO
Trigger Level
5
Interrupt)
RTS High
Threshold
RTS Low
Threshold
RX FIFO
12 _{Trigger Level}
RTSCTS1
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
3.3 Infrared Mode
Each UART in the V352 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.1. The input pin ENIR conveniently activates both UART channels to start up in the
infrared mode. This global control pin enables the MCR bit [6] function in every UART channel register. After
power up or a reset, the software can overwrite MCR bit [6] if so desired. ENIR and MCR bit [6] also disable its
receiver while the transmitter is sending data. This prevents the echoed data from going to the receiver. The
global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current
while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[1:0], would
idle LOW. Likewise, the RX [1:0] inputs assume a LOW idle level.
The infrared encoder sends out a 3/16 of a bit wide pulse for each “0” bit in the transmit data stream. This
signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See
Figure 12 below. Typical max data rate for the infrared encoder with a 3/16 of a bit wide pulse is 115.2 kbps.
For data rates above 115.2 kbps and up to1.152 Mbps, Fast IR mode can be enabled via DLD bit-4 for a 1/4 of
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