XR17V352IB-0A-EVB Datasheet, PDF (1/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
APRIL 2015
REV. 1.0.4
GENERAL DESCRIPTION
The XR17V352¹ (V352) is a single chip 2-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V352 serves as a
single lane PCIe bridge to 2 independent enhanced
16550 compatible UARTs. The V352 is compliant to
PCIe 2.0 Gen 1 (2.5 GT/s).
In addition to the UART channels, the V352 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V352 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
31.25 Mbps. The V352 is available in a 113-pin
FPBGA package (9 x 9 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
 Next generation Point-of-Sale Systems
 Remote Access Servers
 Storage Network Management
 Factory Automation and Process Control
 Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
 Single 3.3V power supply
 Internal buck regulator for 1.2V core
 PCIe 2.0 Gen 1 compliant
 x1 Link, dual simplex, 2.5 Gbps in each direction
 EEPROM interface for configuration
 Data read/write 32-bit operation
 Global interrupt status register for both UARTs
 Up to 31.25 Mbps serial data rate
 16 multi-purpose inputs/outputs (MPIOs)
 16-bit general purpose timer/counter
 Sleep mode with wake-up Indicator
 Two independent UART channels controlled with
■ 16550 compatible register Set
■ 256-byte TX and RX FIFOs
■ Programmable TX and RX Trigger Levels
■ TX/RX FIFO Level Counters
■ Fractional baud rate generator
■ Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■ Automatic Xon/Xoff software flow control
■ RS-485 half duplex direction control output
with programmable turn-around delay
■ Multi-drop with Auto Address Detection
■ Infrared (IrDA 1.1) data encoder/decoder
 Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
FIGURE 1. BLOCK DIAGRAM OF THE XR17V352
TX+
TX-
RX+
RX-
CLK+
CLK-
CLKREQ#
RST#
EN485#
E N IR #
EECK
EEDI
EEDO
EECS
C o n fig u ratio n
Space
R eg isters
B uck R egulator
PInCtPIeCLr _fIoaeccael
Bus
In te rfa c e
C o n fig u ratio n
E_RE_eSP_gpiR^ascO_{t ee}M_{r s}
In te rfa c e
125 M H z C lo ck
G lobal
C onfiguration
R egisters
1166-- b it
TTimimeer /rC/Coouunnteter r
UUAARRTTCChhaannnneel ^l00
64- b yte TX FIFO
U A R T 256-b yte T X F IF O
URAeRg Ts
R eg s
BRG
TX & RX
TX & RX
64- byte
IR
EE NNIRDD EE CC
REXNFDIEF OC
B R G 256-b yte R X F IF O
UART Channel 2
UART Channel 1
256-b yte TX FIFO
UART
Regs
UA
TX
RT
&
C
RX
ha
n
IR
E_nN_eD_l
E₅
C
B RUGA R2 5T6 -Cb yhtae nRnX eFlIF6O
M u lti-p u rp o se
In p u t s- /O u tp u ts
In p u ts/O u tp u ts
C rystal O sc/B uffer
TT XX [[ 71 :: 00 ]]
R X [1:0]
R X [7:0]
R TS#[1:0]
D T R #[1:0]
C T S #[1:0]
D S R #[1:0]
D C D #[1:0]
R I#[1:0]
M P IO [15:0]
TM RCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com