XR17V352IB-0A-EVB Datasheet, PDF (5/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

REV. 1.0.4
PIN DESCRIPTIONS
NAME
MPIO10
PIN #
L2
MPIO11
K3
MPIO12
L3
MPIO13
J4
MPIO14
K4
MPIO15
L5
EEPROM SIGNALS
EECK
J7
EECS
K8
EEDI
J8
EEDO
L9
JTAG SIGNALS
TRST#
L6
TCK
K6
TMS
J6
TDI
L7
TDO
K7
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
TYPE
DESCRIPTION
I/O Multi-purpose input/output 10. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
I/O Multi-purpose input/output 11. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
I/O Multi-purpose input/output 12. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
I/O Multi-purpose input/output 13. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
I/O Multi-purpose input/output 14. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
I/O Multi-purpose input/output 15. This pin defaults to an input with interrupts dis-
abled and is controlled using the MPIOSEL, MPIOLVL, MPIOINV, MPIO3T,
MPIOOD and MPIOINT configuration registers. If unused, a pull-up or pull-
down resistor is recommended on this pin.
O Serial clock output uses the internal 125 MHz clock divided by 256 (488 KHz)
following power-up or reset to read an external EEPROM. This pin may also
be manually clocked using the Configuration Register REGB.
I/O Active high chip select output to an external EEPROM with internal weak pull-
down resistor. Connect an external 4.7K ohm pull-up resistor to this pin to
enable reading of an external EEPROM. This pin may also be manually
enabled using the Configuration Register REGB.
O Write data to EEPROM device. It is manually accessible using the Configura-
tion Register REGB.
I Read data from EEPROM device with internal pull-down resistor. It is manu-
ally accessible using the Configuration Register REGB.
I JTAG Test Reset. This signal is active LOW with internal pull-up resistor
I JTAG Test Clock
I JTAG Test Mode Select with internal pull-up resistor
I JTAG Data Input with internal pull-up resistor
O JTAG Data Output
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