XR17V352IB-0A-EVB Datasheet, PDF (10/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. 1.0.4
ADDRESS
OFFSET
BITS
0x00 31:16
15:0
0x04 31
30
29:28
27
26:25
24
23
22
21
20
19:16
15:11,
9,7, 5,
4, 3, 2
10
8
6
1
0
0x08
0x0C
0x10
31:8
7:0
31:24
23:16
15:8
7:0
31:11
10:0
0x14 31:0
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
TYPE
DESCRIPTION
EWR
EWR
RWC
RWC
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Device ID
Vendor ID (Exar) specified by PCISIG
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
Target Abort.
DEVSEL# timing.
Unimplemented bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bit
66MHz capable
Capabilities List
Reserved Status bits
Command bits (reserved)
RESET VALUE
(HEX OR BINARY)
0x0352
0x13A8
0b
0b
00b
0b
00b
0b
0b
0b
0b
1b
0000b
0x0000
RWR
RWR
RWR
RWR
RO
EWR
RO
RO
RO
RO
RO
RWR
RO
RWR
This bit disables the device from asserting INTx#. logic 1 = dis-
0b
able assertion of INTx# and logic 0 = enables assertion of INTx#
SERR# driver enable. logic 1=enable driver and 0=disable driver
0b
Parity error enable. logic 1=respond to parity error and 0=ignore
0b
Command controls a device’s response to mem space accesses:
0b
0=disable mem space accesses, 1=enable mem space accesses
Device’s response to I/O space accesses is disabled.
0b
(0 = disable I/O space accesses)
Class Code (Default is ’Simple 550 Communication Controller’)
0x070002
Revision ID (Exar device revision number)
Current Rev. value
BIST (Built-in Self Test)
0x00
Header Type (a single function device with one BAR)
0x00
Unimplemented Latency Timer (needed only for bus master)
0x00
Unimplemented Cache Line Size
0x00
Memory Base Address Register (BAR0)
0x00000
Claims an 2K address space for the memory mapped UARTs
including the UARTs on the expansion interface.
0x0000
Unimplemented Base Address Register (returns zeros)
0x00000000
10