XR17V352IB-0A-EVB Datasheet, PDF (24/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. 1.0.4
The 8-bit SLEEP register enables each UART separately to enter Sleep mode. The SLEEP register is
accessible from the Device Configuration Registers in all UART channels but the UART channel can only
control the bit for that channel. For example, writing 0xFF to the SLEEP register in channel 0 will only enable
the sleep mode for channel 0.
Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. The UART enters
sleep mode when the following conditions are satisfied after the sleep mode is enabled (Logic 0 (default) is to
disable and logic 1 is to enable sleep mode):
■ Transmitter and Receiver are empty (LSR[6]=1, LSR[0]=0)
■ RX pin is idling at a HIGH in normal mode or a LOW in infrared mode
■ The modem inputs (CTS#, DSR#, CD# and RI#) are steady at either HIGH or LOW (MSR bits [3:0] =
0x0)
The V352 is awakened by any of the following events occurring at any of the 2 UART channels:
■ A receive data start bit transition (HIGH to LOW in normal mode or from LOW to HIGH in infrared mode)
■ A data byte is loaded into the transmitter
■ A change of logic state on any of the modem inputs so that any of the delta bits (MSR bits[3:0]) is set
(RI# delta bit is only set on the rising edge)
A receive data start bit transition will not wake up the UART if the Multidrop mode is disabled (DLD[6] = 0) and
the receiver is disabled (MSR[2] = 1, MSR[0] = 0).
A special interrupt is generated with an indication of no pending interrupt. The V352 will return to sleep mode
automatically after all interrupting conditions have been serviced and cleared. It will stay in the sleep mode of
operation until it is disabled by resetting the SLEEP register bits.
1.4.6 Device Identification and Revision
There are two internal registers that provide device identification and revision, DVID and DREV registers. The
8-bit content in the DVID register provides device identification. A return value of 0x82 from this register
indicates the device is a XR17V352. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02
equals to revision B and so on. This information is very useful to the software driver for identifying which device
it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The Device ID of the XR17V352 is 0x82.
DREV [7:0]
Revision number of the XR17V352. A 0x01 represents "revision-A" with 0x02 for rev-B and so on.
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to both UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data in an external EEPROM.
1.4.7 REGB Register
REGB[16](Read/Write)
REGB[17](Read/Write)
REGB[18](Read/Write
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to both UARTs configuration register.
Logic 0 (default) - wake-up interrupt is generated when UART exits sleep mode.
Logic 1 - No wake-up interrupt is generated when UART exits sleep mode.
Logic 0 (default) - Global interrupt enable. Interrupts to PCI host are enabled.
Logic 1 - Global interrupt disable. Interrupts to PCI host are disabled.
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