XR17V352IB-0A-EVB Datasheet, PDF (25/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

REV. 1.0.4
1.4.7 REGB Register
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REGB[19](Read-Only)
Logic 0 - EEPROM load is valid.
Logic 1 - EEPROM load error caused by one of the following conditions: EEPROM not
attached, final bit not found, parity error detected.
REGB[20] (Write-Only)
Control the EECK, clock, output on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output to the EEPROM device.
REGB[22] (Write-Only)
EEDI data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO data output. Read data from the EEPROM device.
1.4.8 Multi-Purpose Inputs and Outputs
The V352 provides 16 multi-purpose inputs/outputs MPIO[15:0] for general use. Each pin can be programmed
to be an input or output function. The input logic state can be set for normal or inverted level, and optionally set
to generate an interrupt. The outputs can be set to be normal HIGH or LOW state, 3-state, or open drain. Their
functions and definitions are programmed through 6 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV,
MPIOSEL, and MPIOOD. If all 16 pins are set for inputs, all 16 interrupts would be ORed together. The ORed
interrupt is reported in the channel 0 UART interrupt status, see Interrupt Status Register. The pins may also be
programmed to be outputs and to the 3-state condition for signal sharing. The MPIO[0] pin can be programmed
to show the Timer output. When it is programmed to be the Timer output, all the above 5 registers lose control
over the MPIO[0] pin. For details on Timer output, please see “Section 1.4.2, General Purpose 16-bit Timer/
Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00)” on page 19.
1.4.9 MPIO REGISTERS
There are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs.
Figure 9 shows the internal circuitry.
FIGURE 9. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
MPIOINT [15:0]
IN T
AND
Rising Edge
D e te c tio n
AND
MPIOLVL [15:0]
Read Input Level
MPIOINV [15:0]
(Input Inversion Enable =1)
MPIOLVL [15:0]
(O utput Level)
MPIOOD [15:0]
(Open-Drain Enable =1)
MPIO3T [15:0]
(3-state Enable =1)
MPIO SEL [15:0]
(Select Input=1, Output=0 )
AND
1
0
OR
M P IO
Pin [15:0]
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