XR17V352IB-0A-EVB Datasheet, PDF (22/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
FIGURE 7. TIMER OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES
TIMER Output in
One-Shot Mode
START TIMER
COMMAND ISSUED
START TIMER COMMANDS ISSUED: LESS THAN 'N'
CLOCKS BETWEEN SUCCESSIVE COMMANDS
START TIMER
COMMAND ISSUED
'N' Clocks
< 'N' Clocks
< 'N' Clocks
STOP TIMER
COMMAND ISSUED
REV. 1.0.4
TIMER Output in
Re-triggerable
Mode
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'Q'
clocks
After 'Q'
clocks
After 'Q'
clocks
After 'Q'
clocks
Timer Interrupt
In the one-shot mode, the Timer will issue an interrupt upon timing out which is ’N’ clocks after the Timer is
started. In the re-triggerable mode, the Timer will keep issuing an interrupt every ’N’ clocks which is on every
rising edge of the Timer output. The Timer interrupt can be cleared by reading the TIMERCNTL register or
when a Timer Reset command is issued which brings the Timer back to its default settings. The TIMERCNTL
will read a value of 0x01 when the Timer interrupt is enabled and there is a pending interrupt. It reads a value
of 0x00 at all other times. Stopping the Timer does not clear the interrupt and neither does subsequent re-
starting.
FIGURE 8. INTERRUPT OUTPUT (ACTIVE LOW) IN ONE-SHOT AND RE-TRIGGERABLE MODES
Timer Started
Timer Timed
Out
TIMERCNTL
read
One-shot Mode
Timer Timed TIMERCNTL Timer Timed
Out
read
Out
Re-triggerable
Mode
1.4.3 8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel. The 8XMODE register is accessible from the
Device Configuration Registers in all UART channels but the UART channel can only control the bit for that
channel. For example, bit [0] is for channel 0 and can only be controlled by channel 0. All other bits are read-
only in channel 0. Logic 0 (default) selects normal 16X sampling (and 4XMODE = 0x00) with logic one selects
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