XR17V352IB-0A-EVB Datasheet, PDF (52/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode)
REV. 1.0.4
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit [6]. DTR# selection is associated with DSR# and RTS# is with CTS#.
 Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
 Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR
register, as shown in Figure 13.
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If
the modem interface is not used, this output may be used for general purpose.
 Logic 0 = Force RTS# output to a HIGH (default).
 Logic 1= Force RTS# output to LOW.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit [6] and MCR bit [2]=1. If
the modem interface is not used, this output may be used for general purpose.
 Logic 0 = Force DTR# output to a HIGH (default).
 Logic 1 = Force DTR# output to a LOW.
4.9 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit [2] is set to a
logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
 Logic 0 = No FIFO error (default).
 Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR,
in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the
TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new
character for transmission. This bit is set to a logic HIGH when the last data byte is transferred from the
transmit FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the
transmit FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is
cleared when at a byte is written to the THR.
LSR[4]: Receive Break Flag
 Logic 0 = No break condition (default).
 Logic 1 = The receiver received a break signal (RX was LOW for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or HIGH.
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