XR17V352IB-0A-EVB Datasheet, PDF (49/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

REV. 1.0.4
TRIGGER
TABLE
Table-C
Table-D
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
TABLE 15: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCTR FCTR FCR FCR FCR FCR
RECEIVE
BIT [7] BIT [6] BIT [7] BIT [6] BIT [5] BIT [4] TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
1
0
0
0
0
1
1
0
1
1
0
0
8
0
1
16
1
0
56
1
1
60
8
16C654
16
32
56
1
1
X
X
X
X Programmable Programmable 16L2752, 16L2750,
via RXTRG
via TXTRG ^{16C2852, 16C850,}
register
register
16C854, 16C864
4.7 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM, DLD) enable.
 Logic 0 = Data registers are selected (default).
 Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW, state). This condition remains until disabled by setting LCR bit [6] to a logic 0.
 Logic 0 = No TX break condition. (default)
 Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit [5] selects the forced parity format.
 LCR bit [5] = logic 0, parity is not forced (default).
 LCR bit [5] = logic 1 and LCR bit [4] = logic 0, parity bit is forced to a logical 1for the transmit and receive
data.
 LCR bit [5] = logic 1 and LCR bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
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