XRT73LC00A_08 Datasheet, PDF (50/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
FIGURE 28. THE DIGITAL LOCAL LOOP-BACK PATH IN THE XRT73LC00A
RTIP
RRING
REQDIS
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
TTIP
TRING
TXLEV
TXOFF
DMO
RLOL EXCLK
AGC/
Equalizer
Slicer
Clock
Recovery
Peak
Detector
LOS Detector
Serial
Processor
Interface
Digital Local
Loop-Back Path
Data
Recovery
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
MTIP
MRING
The Digital Local Loop-Back Mode, along with the TxOFF feature, is useful in Redundancy System Design.
These two features permit the system to execute some diagnostic tests in the Back-up Line Card without
transmitting data onto the line and interfering with the DS3/E3/STS-1 traffic from the Primary Line Card.
The XRT73LC00A can be configured to operate in the Digital Local Loop-Back Mode by employing either one
of the following two-steps.
A. If the XRT73LC00A is operating in the HOST Mode
Access the Microprocessor Serial Interface and write a “1” into both the LLB and RLB bit-fields in Command
Register 4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
X STS-1/DS3
E3
X
X
X
D1
D0
LLB
RLB
1
1
B. If the XRT73LC00A is operating in the Hardware Mode
Set both the LLB input pin (pin 14) and the RLB input pin (pin 15) to “High”.
NOTES:
1. The Digital Local Loop-Back Mode feature works even if the transmitter is turned off via the TXOFF feature.
2. The XRT73LC00A automatically declares an LOS Condition any time it has been configured to operate in either
the Analog Local Loop-Back or Digital Local Loop-Back Modes. Consequently, the Muting -upon -LOS must be
disabled prior to configuring the device to operate in either of these local Loop-Back modes.
4.3 The Remote Loop-Back Mode
When the XRT73LC00A is configured to operate in the Remote Loop-Back Mode, it ignores any signals that
are input to the TPDATA and TNDATA input pins. The XRT73LC00A receives the incoming line signal via the
RTIP and RRING input pins. This data is processed through the Receive Section of the XRT73LC00A and
outputs to the Receive Terminal Equipment via the RPOS, RNEG, RCLK1 and RCLK2 output pins.
Additionally, this data is internally looped back into the Pulse-Shaping block in the Transmit Section. At this
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