XRT73LC00A_08 Datasheet, PDF (41/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
FIGURE 19. AN EXAMPLE OF HDB3 DECODING
Line Signal
00 0 V
RCLK
B 00 V
RPOS
RNEG
Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
NOTE: If the HDB3 Decoder detects any bipolar violation (e.g., “V”) pulses that is not in accordance with the HDB3 Line
Code format, or if the HDB3 Decoder detects a string of 4 (or more) “0’s” in the incoming line signal, then the HDB3
Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High”.
3.5.3 Enabling/Disabling the HDB3/B3ZS Decoder
The HDB3/B3ZS Decoder of the XRT73LC00A can be enabled or disabled by either of the following means:
If the XRT73LC00A is operating in the Hardware Mode:
Enable the HDB3/B3ZS Encoder/Decoder by pulling the ENDECDIS input pin (pin 21) to GND. To disable the
HDB3/B3ZS Encoder/Decoder, pull the ENDECDIS input pin to VDD.
If the XRT73LC00A is operating in the HOST Mode:
Enable the XRT73LC00A HDB3/B3ZS Encoder/Decoder by writing a “0” into the ENDECDIS bit-field in
Command Register CR2. To disable the HDB3/B3ZS Encoder/Decoder, write a “1” into the ENDECDIS bit-
field.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
0
X
X
X
3.6 LOS Declaration/Clearance
The XRT73LC00A contains circuitry that monitors the following two parameters associated with the incoming
line signals.
1. The amplitude of the incoming line signal via the RTIP and RRING inputs; and
2. The number of pulses detected in the incoming line signal within a certain amount of time.
If the XRT73LC00A determines that the incoming line signal is missing due to insufficient amplitude or a lack of
pulses in the incoming line signal) then it declares a Loss of Signal (LOS) condition. The XRT73LC00A
declares the LOS condition by toggling the RLOS output pin “High” and by setting the RLOS bit field in
Command Register 0 to “1”.
If the XRT73LC00A determines that the incoming line signal has been restored (e.g., there is sufficient
amplitude and pulses in the incoming line signal) then it clears the LOS condition by toggling the RLOS output
pin “Low” and setting the RLOS bit-field to “0”.
The LOS Declaration/Clearance scheme that is employed in the XRT73LC00A is based upon ITU-T
Recommendation G.775 for both E3 and DS3 applications. The LOS Declaration and Clearance criteria that
the XRT73LC00A uses for each of these modes (e.g., E3 and DS3) are presented below.
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