XRT73LC00A_08 Datasheet, PDF (39/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
The only time the Receive Equalizer should be disabled is when there is an off-chip equalizer in the Receive
path between the DSX-3/STSX-1 Cross-Connect and the RTIP/RRING input pins or, in applications where the
Receiver is monitoring the transmit output signal directly.
3.2.1.1.2
Design Considerations for E3 Applications
In E3 system installation, it is recommended that the Receive Equalizer of the XRT73LC00A be enabled by
pulling the REQDIS input pin to GND or by setting the REQDIS bit-field to “0”.
NOTE: The results of extensive testing indicates that when the Receive Equalizer is enabled, the XRT73LC00A is capable
of receiving an E3 line signal with anywhere from 0 to 12dB of cable loss over the Industrial Temperature range.
Design Considerations if the Overall Cable Length is known
If during system installation the overall cable length is known, then in order to optimize the performance of the
XRT73LC00A in terms of receive intrinsic jitter, etc., the Receive Equalizer should be enabled or disabled
based upon the following recommendations:
The Receive Equalizer should be turned ON if the Receive Section is going to receive a line signal with an
overall cable length of 300 feet or greater. The Receive Equalizer should be turned OFF if the Receive Section
is going to receive a line signal over a cable length of less than 300 feet.
NOTES:
1. If the Receive Equalizer block is turned ON in a given Receive Section that is receiving a line signal over short
cable length, there is the risk of over-equalizing the received line signal which could degrade performance by
increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors.
2. The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal
experiences as it travels from the Transmitting Terminal to the Receiving Terminal. However, Receive Equalizer
was not designed to counter flat loss where all of the Fourier frequency components in the line signal are subject
to the same amount of attenuation. Flat loss is handled by the AGC block.
The Receive Equalizer block can be disabled setting the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bit-field in Command Register CR2 when operating the
XRT73LC00A in the HOST Mode.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
X
X
X
1
3.3 Peak Detector and Slicer
After the incoming line signal has passed through the Receive Equalizer, it is routed to the Slicer block. The
purpose of the Slicer is to quantify a given bit-period or symbol within the incoming line signal as either a “1” or
a “0”.
3.4 Clock Recovery PLL
The output of the Slicer, which is now Dual-Rail digital pulses, is routed to the Clock Recovery PLL. The
purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate
a recovered clock signal.
It is important to note that the Clock Recovery PLL requires a line rate clock signal at the EXCLK input pin.
The Clock Recovery PLL operates in one of two modes:
• The Training Mode.
• The Data/Clock Recovery Mode
1. The Training Mode
If the XRT73LC00A is not receiving a line signal via the RTIP and RRING input pins or if the frequency
difference between the line signal and that applied via the EXCLK input pin exceeds 0.5%, then the
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