XRT73LC00A_08 Datasheet, PDF (46/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
FIGURE 22. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT73LC00A TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RxNEG
RCLK1, 2
RPOS
RNEG
Receive
Logic
RCLK1, 2 ^Block
Exar E3/DS3/STS-1 LIU
The manner that the LIU transmits Dual-Rail data to the Receiving Terminal Equipment is described below and
illustrated in Figure 23. The XRT73LC00A typically updates the data on the RPOS and RNEG output pins on
the rising edge RCLK1 (or RCLK2).
FIGURE 23. HOW THE XRT73LC00A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG
RCLK1
RCLK1 (or RCLK2) is the Recovered Clock signal from the incoming Received line signal. These clock signals
are typically 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications and 51.84 MHz for SONET
STS-1 applications.
If the XRT73LC00A received a positive-polarity pulse in the incoming line signal via the RTIP and RRING input
pins, then the XRT73LC00A pulses the RPOS output pin “High”. If the XRT73LC00A received a negative-
polarity pulse in the incoming line signal via the RTIP and RRING input pins, then the XRT73LC00A pulses the
RNEG output pin “High”.
Inverting the RCLK1 or RCLK2 outputs
When using the XRT73LC00A, either of the RCLK1 or RCLK2 signals can be inverted with respect to the
delivery of the RPOS and RNEG output signals to the Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of RCLK1 or RCLK2. Figure 24 illustrates the behavior of the
RPOS, RNEG and RCLK signals when the RCLK signal has been inverted.
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