XRT73LC00A_08 Datasheet, PDF(49/63 Page) Exar Corporation

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XRT73LC00A_08 Datasheet, PDF (49/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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XRT73LC00A

E3/DS3/STS-1 LINE INTERFACE UNIT

FIGURE 27. THE ANALOG LOCAL LOOP-BACK IN THE XRT73LC00A

RLOL EXCLK

RTIP

RRING

REQDIS

LOSTHR

SDI

SDO/LCV

SCLK

REGRESET

TTIP

TRING

TXLEV

TXOFF

DMO

AGC/

Equalizer

Slicer

Clock

Recovery

Peak

Detector

LOS Detector

Data

Recovery

Serial

Processor

Interface

Analog Local

Loop-Back Path

Loop MUX

Invert

HDB3/

B3ZS

Decoder

Pulse

Shaping

HDB3/

B3ZS

Encoder

Device

Monitor

Transmit

Logic

Duty Cycle Adjust

REV. 1.0.1

RCLK1

RCLK2

RPOS

RNEG

DR/SR

RLOS

LLB

RLB

ENDECDIS

TAOS

TPDATA

TNDATA

TCLK

MTIP

MRING

If the XRT73LC00A is operating in the HOST Mode:

Access the Microprocessor Serial Interface and write a â1â into the LLB bit-field and a â0â into the RLB bit-field

in Command Register 4.

COMMAND REGISTER CR4 (ADDRESS = 0X04)

X STS-1/DS3

LLB

RLB

If the XRT73LC00A is operating in the Hardware Mode:

The LLB input pin (pin 14) must be set to âHighâ and the RLB input pin (pin 15) must be set to âLowâ.

NOTES:

1. The Analog Local Loop-Back Mode does not work if the transmitter is turned off via the TXOFF feature.

2. The XRT73LC00A automatically Declares an LOS Condition anytime it has been configured to operate in either

the Analog Local Loop-Back or Digital Local Loop-Back Modes. Consequently, the Muting -upon -LOS must be

disabled prior to configuring the device to operate in either of these local Loop-Back modes.

4.2 The Digital Local Loop-Back Mode

When the XRT73LC00A is configured to operate in the Digital Local Loop-Back Mode, it ignores any signals

that are input to the RTIP and RRING input pins. The Transmitting Terminal Equipment transmits clock and

data into the XRT73LC00A via the TPDATA, TNDATA and TCLK input pins. This data is processed through the

Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS Encoder block and then looped back to the HDB3/

B3ZS Decoder block.

Figure 28 illustrates the path that the data takes when the chip is configured to operate in the Digital Local

Loop-Back Mode.

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