XRT73LC00A_08 Datasheet, PDF (30/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
B. access the Microprocessor Serial Interface and write a “1” into the TXBIN (TRANSMIT BINary) bit-field in
Command Register 1.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS TXCLKINV TXLEV TXBIN
X
X
X
X
1
After taking these steps, the Transmit Logic Block accepts Single-Rail data via the TPDATA input pin. The
XRT73LC00A samples this input pin on the falling edge of the TCLK clock signal and encodes it into the
appropriate bipolar line signal across the TTIP and TRING output pins.
NOTES:
1. In this mode the Transmit Logic Block ignores the TNDATA input pin.
2. If the Transmit Section of the XRT73LC00A is configured to accept Single-Rail data from the Terminal Equipment,
the B3ZS/HDB3 Encoder must be enabled.
Figure 11 illustrates the behavior of the TPDATA and TCLK signals when the Transmit Logic Block has been
configured to accept Single-Rail data from the Terminal Equipment.
FIGURE 11. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
TPDATA
TCLK
1
1
0
0
2.2 The Transmit Clock Duty Cycle Adjust Circuitry
The on-chip Pulse-Shaping circuitry in the Transmit Section of the XRT73LC00A has the responsibility for
generating pulses of the shape and width to comply with the applicable pulse template requirement. The
widths of these output pulses are defined by the width of the half-period pulses in the TCLK signal.
Allowing the widths of the pulses in the TCLK clock signal to vary significantly could jeopardize the chip’s ability
to generate Transmit Output pulses of the appropriate width, thereby failing the applicable Pulse Template
Requirement Specification. The chips ability to generate compliant pulses could depend upon the duty cycle of
the clock signal applied to the TCLK input pin.
In order to combat this phenomenon, the Transmit Clock Duty Cycle Adjust circuit was designed into the
XRT73LC00A. The Transmit Clock Duty Cycle Adjust Circuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging from 30% to 70% and to regenerate these signals with a
50% duty cycle.
The XRT73LC00A Transmit Clock Duty Cycle Adjust circuit alleviates the need to supply a signal with a 50%
duty cycle to the TCLK input pin.
2.3 The HDB3/B3ZS Encoder Block
The purpose of the HDB3/B3ZS Encoder Block is to aid in the Clock Recovery process at the Remote Terminal
Equipment by ensuring an upper limit on the number of consecutive zeros that can exist in the line signal.
2.3.1 B3ZS Encoding
If the XRT73LC00A is configured to operate in the DS3 or SONET STS-1 Modes, then the HDB3/B3ZS
Encoder block operates in the B3ZS Mode. When the Encoder is operating in this mode, it parses through and
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