XRT73LC00A_08 Datasheet, PDF (48/63 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
FIGURE 25. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT73LC00A TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RPOS
RCLK1, 2 RCLK1, 2
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
FIGURE 26. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT73LC00A IS TRANSMIT-
TING SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS
RCLK1
4.0 DIAGNOSTIC FEATURES OF THE XRT73LC00A
The XRT73LC00A supports equipment diagnostic activities by supporting the following Loop-Back modes in
the chip:
• Analog Local Loop-Back
• Digital Local Loop-Back
• Remote Loop-Back.
4.1 The Analog Local Loop-Back Mode
When the XRT73LC00A is configured to operate in the Analog Local Loop-Back Mode, the XRT73LC00A
ignores any signals that are input to the RTIP and RRING input pins. The Transmitting Terminal Equipment
transmits clock and data into the XRT73LC00A via the TPDATA, TNDATA and TCLK input pins. This data is
processed through the Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS Encoder. Finally, this data
outputs to the line via the TTIP and TRING output pins and is looped back into the AGC/Receive Equalizer
Block. Consequently, this data is also processed through the Receive Section of the XRT73LC00A. After this
post-loop-back data has been processed through the Receive Section it outputs to the Near-End Receiving
Terminal Equipment via the RPOS, RNEG, RCLK1 and RCLK2 output pins.
Figure 27 illustrates the path that the data takes when the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT73LC00A can be configured to operate in the Analog Local Loop-Back Mode by employing either one
of the following two steps:
43