XRD98L61 Datasheet, PDF (28/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
Preliminary
CCD Signal
SBLK
SPIX
ADCLK
φ3
Black
Level
Video
Level
Reset Reject
Switches Turn OFF
Figure 17. Pixel Rate Clock Timing with RSTreject=1
Aperture delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are two serial interface registers, DelayA &
DelayB, used to program the aperture delays. Each
register is divided into 3 delay parameters. Each delay
parameter is 3 bits wide. Each delay parameter can be
set to add from 0ns to 7ns of delay.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge depends on the polarity control
bit for each clock. For the default case, SBLKpol=0 &
SPIXpol=0, the leading edge is the falling edge and the
trailing edge is the rising edge.
DelayA[2:0] controls the delay added to the leading
edge of SBLK. This positions the falling edge of
internal signal φ1.
DelayA[5:3] controls the delay added to the trailing
edge of SBLK. This positions the rising edge of
internal signal φ1.
DelayB[2:0] controls the delay added to the leading
edge of φ2. This positions the falling edge of internal
signal φ2.
DelayB[5:3] controls the delay added to the trailing
edge of SPIX. This positions the rising edge of
internal signal φ2.
DelayB[8:6] is only used when SPIXopt=0. It controls
the delay from the trailing edge of SBLK to the start
of the internal φ2 control. This delay is in addition to
DelayA[5:3], the SBLK trailing edge delay.
DelayA[8:6] controls the delay added to ADCLK. This
is a simple delay, it adds the same delay to both the
rising and falling edges of ADCLK to create φ4.
Rev. P4.00
28