XRD98L61 Datasheet, PDF (14/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
Preliminary
Clock
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLKtest Nullamp CMtest Fastclk CLAMPopt Oneshot ClampCal SPIXopt RSTreject VSreject
0
0
0
0
0
0
0
0
0
0
Clock Register (Reg. 10, Address 001010)
The Clock register is used to set various clocking options.
CLKtest=0, Please leave this bit in the default setting.
Nullamp=0, Please leave this bit in the default setting.
CMtest=0, Please leave this bit in the default setting.
Fastclk=0, Please leave this bit in the default setting.
CLAMPopt=0, DC Restore bias is on only during CLAMP.
CLAMPopt=1, DC Restore bias is always ON.
OneShot=0, CAL defines OB pixels. Clamp controls DC restore.
OneShot=1, CAL controls DC restore and defines OB pixels. CLAMP used for VS reject.
ClampCal=0, CLAMP at start of line, CAL at end of line (affects VS reject).
ClampCal=1, CAL at start of line, CLAMP at end of line (affects VS reject).
SPIXopt=0, φ2 starts DelayA[5:3] + DelayB[8:6] after SBLK trailing edge
SPIXopt=1, φ2 starts DelayB[2:0] after SPIX pin leading edge.
RSTreject=0, Reset reject switch (φ3) not clocked, always on.
RSTreject=1, Reset reject switch (φ3) clocked.
VSreject=0, Vertical Shift Reject is inactive.
VSreject=1, Vertical Shift Reject is active.
Delay A
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DelayA[8] DelayA[7] DelayA[6] DelayA[5] DelayA[4] DelayA[3] DelayA[2] DelayA[1] DelayA[0]
0
0
0
0
0
0
0
0
0
0
Delay A Register (Reg. 11, Address 001011)
Delay B
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DelayB[8] DelayB[7] DelayB[6] DelayB[5] DelayB[4] DelayB[3] DelayB[2] DelayB[1] DelayB[0]
0
0
0
0
0
0
0
0
0
0
DelayB Register (Reg. 12, Address 001100)
The DelayA & DelayB registers are used to add internal delay to the pixel rate clocks.
For each 3 bit delay parameter, 000 is minimum delay, 111 is maximum delay (∼7ns).
DelayA[8:6]: ADC Clock delay.
DelayA[5:3]: φ1 trailing edge delay.
DelayA[2:0]: φ1 leading edge delay.
DelayB[8:6]: Delay for SPIX option.
DelayB[5:3]: φ2 trailing edge delay.
DelayB[2:0]: φ2 leading edge delay.
Rev. P4.00
14