XRD98L61 Datasheet, PDF (27/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

Preliminary
XRD98L61
CCD Signal
SBLK
SPIX
ADCLK
φ2
Black Level
Video
Level
DelayB[8:6]
Figure 15. Pixel Rate Clock Timing with SPIXopt=0 (Default)
CCD Signal
SBLK
SPIX
ADCLK
φ2
Black Level
Video
Level
Figure 16. Pixel Rate Clock Timing with SPIXopt=1
Reset Reject
In the default state the reset reject switches (φ3)are
always ON, they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling the
PGA should have enough time to recuperate, but as a
precaution we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse, and turned
ON again at the start of the SBLK pulse. This will
effectively reject the reset pulse and prevent it from
railing the PGA.
Rev. P4.00
27