XRD98L61 Datasheet, PDF (15/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

Preliminary
XRD98L61
DAC0
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC0[7] DAC0[6] DAC0[5] DAC0[4] DAC0[3] DAC0[2] DAC0[1] DAC0[0]
0
0
0
0
0
0
0
0
0
0
DAC0 Register (Reg. 13, Address 001101)
DAC1
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC1[7] DAC1[6] DAC1[5] DAC1[4] DAC1[3] DAC1[2] DAC1[1] DAC1[0]
0
0
0
0
0
0
0
0
0
0
DAC1 Register (Reg. 14, Address 001110)
The DAC1 & DAC0 registers are used to program
the two 8-bit Utility DACs.
Code 00000000 is minimum output voltage.
Code 11111111 is maximum output voltage.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ReadBack RBenable RBreg[8] RBreg[7] RBreg[6] RBreg[5] RBreg[4] RBreg[3] RBreg[2] RBreg[1] RBreg[0]
Default
0
0
0
0
0
0
0
0
0
0
Readback Register (Reg. 62, Address 111110)
The readback register is used to enable the readback
function and select a register for readback.
RBenable=0, Readback disabled.
RBenable=1, Readback enabled. Contents of se-
lected register is output on DB[11:2] pins.
RBreg[8:0], select register to read from, see table in
Serial Interface Read Back section.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
Reset
Default
0
0
0
0
0
0
0
0
0
0
Reset Register (Reg. 63, Address 111111)
The Reset register is used to reset the entire chip.
Reset=0, Normal operation.
Reset=1, Resets the chip. The Reset bit will automatically reset after approximately 10 ns delay.
Rev. P4.00
15