XRD98L61 Datasheet, PDF (26/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
Preliminary
CCD
Signal
Pixel N
Black Level
Video
Level
Pixel N+1
Sample
Black
SBLK
SPIX
Sample
Video
ADCLK
DB[11:0] Pixel N-8
Sample ^{bit 11} bit 10
bit 9
PGAout
Pixel N-7
Pixel N-6
bit 8
bit 7
bit 6
bit 5
Pixel N-5
Pixel N-4
7.5 Pixel Pipeline Delay
bit 4
bit 3
Pixel N-3
bits
bit 2
1&0
Pixel N-2
Error
Correction
t_DL
Pixel N-1
Pixel N
Figure 14. Pixel Timing Showing Pipeline Delay
SPIXopt
In the default case below,(Figure 15), SPIXopt=0, the
internal sample video switches turn ON a programmed
delay after the SBLK pulse ends, and turn OFF at the
end of the SPIX pulse. The turn ON delay is pro-
grammed by DelayB[8:6].
When SPIXopt = 1, the internal SPIX switches are
controlled only by the SPIX pulse. This mode is
intended for camera systems where the designer has
the ability to externally fine tune both the rising and
falling edges of SPIX to achieve optimum performance
(see Figure 16).
Rev. P4.00
26