XRD98L61 Datasheet, PDF (25/37 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

Preliminary
XRD98L61
Pixel Rate CLOCKS
SBLK, SPIX & ADCLK
CCD
t_BK
Signal
SBLK
t_PW1
SPIX
t_PIX
Black Sample Point
t_VD
Video Sample Point
t_PW2
ADCLK
t_DL
DB[11:0]
Figure 13. Detailed Pixel Rate Clock Timing for Default Register Settings
Note:
The timing descriptions in this section are correct for
the default conditions: All Polarity bits = 0,
RSTreject = 0 (switch always ON),
SPIXopt = 0
Sampling of the pixel Black Level is controlled by the
SBLK pulse. When SBLK is low, the internal sample
Black switches in the CDS are ON, sampling the pixel
black level on the internal capacitors.
The AFE starts tracking the pixel Video Level an
internal delay after the rising edge of SBLK. The
internal delay is programmed by DelayB[8:6]. The
AFE holds the pixel Video Level on the rising edge of
SPIX.
The ADC will track the PGA output when ADCLK is
high. The ADC will hold the PGA output and start a
conversion when ADCLK goes low. The falling edge of
ADCLK should happen coincident with, or just before
the rising edge of SBLK. ADCLK should be as close as
possible to 50% duty cycle.
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchro-
nized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the
coresponding data is available at the digital output.
Rev. P4.00
25