LM3S610 Datasheet, PDF (75/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Power-On and Brown-Out Reset Control (PBORCTL)
Offset 0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BORTIM
BORIOR BORWT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Bit/Field
31:16
15:2
Name
reserved
BORTIM
1
BORIOR
0
BORWT
Type
RO
R/W
R/W
R/W
Reset
0
0x1FFF
0
1
Description
Reserved bits return an indeterminate value, and should
never be changed.
This field specifies the number of internal oscillator clocks
delayed before the BOR output is resampled if the BORWT
bit is set.
The width of this field is derived by the t_BOR width of 500 µs
and the internal oscillator (IOSC) frequency of 15 MHz ±
50%. At +50%, the counter value has to exceed 10,000.
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the
controller. If set, a reset is signaled. Otherwise, an interrupt
is signaled.
BOR Wait and Check for Noise
This bit specifies the response to a brown-out signal
assertion. If BORWT is set to 1, the controller waits BORTIM
IOSC periods before resampling the BOR output, and if
asserted, it signals a BOR condition interrupt or reset. If the
BOR resample is deasserted, the cause of the initial
assertion was likely noise and the interrupt or reset is
suppressed. If BORWT is 0, BOR assertions do not resample
the output and any condition is reported immediately if
enabled.
April 27, 2007
75
Preliminary