LM3S610 Datasheet, PDF (310/409 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
14
14.1
Inter-Integrated Circuit (I²C) Interface
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire
design (a serial data line SDL and a serial clock line SCL).
The I²C bus interfaces to external I²C devices such as serial memory (RAMs and ROMs),
networking devices, LCDs, tone generators, and so on. The I²C bus may also be used for system
testing and diagnostic purposes in product development and manufacture.
The Stellaris I²C module provides the ability to communicate to other IC devices over an I²C bus.
The I²C bus supports devices that can both transmit and receive (write and read) data.
Devices on the I²C bus can be designated as either a master or a slave. The I²C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I²C modes are: Master Transmit, Master
Receive, Slave Transmit, and Slave Receive.
The Stellaris I²C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I²C master and slave can generate interrupts. The I²C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I²C slave generates
interrupts when data has been sent or requested by a master.
Block Diagram
Figure 14-1. I²C Block Diagram
14.2
Interrupt
I²C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICR
I²C Master Core
I2CSCL
I2CSDA
I²C Slave Core
I2CSCL
I2CSDA
I²C I/O Select
I2CSCL
I2CSDA
Functional Description
The I²C module is comprised of both a master and slave function. The master and slave functions
are implemented as separate peripherals. The I²C module must be connected to bi-directional
Open-Drain pads. A typical I²C bus configuration is shown in Figure 14-2.
See “I2C Timing” on page 395 for I²C timing diagrams.
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April 27, 2007
Preliminary