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LM3S610 Datasheet, PDF (24/409 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
â FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
â Standard asynchronous communication bits for start, stop, and parity
â False-start-bit detection
â Line-break generation and detection
 ADC
â Single- and differential-input configurations
â Two 10-bit channels (inputs) when used as single-ended inputs
â Sample rate of 500 thousand samples/second
â Flexible, configurable analog-to-digital conversion
â Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
â Each sequence triggered by software or internal event (timers, PWM or GPIO)
 I2C
â Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
â Interrupt generation
â Master with arbitration and clock synchronization, multimaster support, and 7-bit
addressing mode
 PWM
â Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
â One 16-bit counter
⢠Runs in Down or Up/Down mode
⢠Output frequency controlled by a 16-bit load value
⢠Load value updates can be synchronized
⢠Produces output signals at zero and load value
â Two comparators
⢠Comparator value updates can be synchronized
⢠Produces output signals on match
â PWM generator
⢠Output PWM signal is constructed based on actions taken as a result of the counter
and comparator output signals
⢠Produces two independent PWM signals
â Dead-band generator
⢠Produces two PWM signals with programmable dead-band delays suitable for driving
a half-H bridge
⢠Can be bypassed, leaving input PWM signals unmodified
â Flexible output control block with PWM output enable of each PWM signal
⢠PWM output enable of each PWM signal
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April 27, 2007
Preliminary
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