LM3S610 Datasheet, PDF (11/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
List of Registers
ARM Cortex-M3 Processor Core ................................................................................................... 34
Register 1: SysTick Control and Status Register......................................................................................... 39
Register 2: SysTick Reload Value Register ................................................................................................. 40
Register 3: SysTick Current Value Register ................................................................................................ 41
System Control ............................................................................................................................... 57
Register 1: Device Identification 0 (DID0), offset 0x000 .............................................................................. 65
Register 2: Device Identification 1 (DID1), offset 0x004 .............................................................................. 66
Register 3: Device Capabilities 0 (DC0), offset 0x008................................................................................. 68
Register 4: Device Capabilities 1 (DC1), offset 0x010................................................................................. 69
Register 5: Device Capabilities 2 (DC2), offset 0x014................................................................................. 71
Register 6: Device Capabilities 3 (DC3), offset 0x018................................................................................. 72
Register 7: Device Capabilities 4 (DC4), offset 0x01C ................................................................................ 74
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................ 75
Register 9: LDO Power Control (LDOPCTL), offset 0x034.......................................................................... 76
Register 10: Software Reset Control 0 (SRCR0), offset 0x040 ..................................................................... 77
Register 11: Software Reset Control 1 (SRCR1), offset 0x044 ..................................................................... 78
Register 12: Software Reset Control 2 (SRCR2), offset 0x048 ..................................................................... 79
Register 13: Raw Interrupt Status (RIS), offset 0x050................................................................................... 80
Register 14: Interrupt Mask Control (IMC), offset 0x054 ............................................................................... 81
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058.......................................................... 83
Register 16: Reset Cause (RESC), offset 0x05C .......................................................................................... 84
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060................................................................. 85
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064 .................................................................... 90
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 ....................................................... 91
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110..................................................... 91
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120........................................... 91
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 ....................................................... 93
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114..................................................... 93
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124........................................... 93
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 ....................................................... 95
Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118..................................................... 95
Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128........................................... 95
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .............................................. 96
Register 29: Clock Verification Clear (CLKVCLR), offset 0x150.................................................................... 97
Register 30: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ....................................... 98
Internal Memory .............................................................................................................................. 99
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ............................................. 105
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134 ........................................ 106
Register 3: USec Reload (USECRL), offset 0x140.................................................................................... 107
Register 4: Flash Memory Address (FMA), offset 0x000 ........................................................................... 108
Register 5: Flash Memory Data (FMD), offset 0x004 ................................................................................ 110
Register 6: Flash Memory Control (FMC), offset 0x008 ............................................................................ 111
Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................. 113
Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 ............................................................. 114
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014......................... 115
April 27, 2007
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