LM3S610 Datasheet, PDF (70/409 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
2
1
0
Name
SWO^a
SWD^a
JTAG^a
Type
RO
RO
RO
Reset
1
1
1
Description
A 1 in this bit indicates the presence of the ARM Serial Wire
Output (SWO) trace port capabilities.
A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
A 1 in this bit indicates the presence of a JTAG port.
a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0
(SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are
not noted are passed as 0. ADCSP is clipped to the maximum value specified in DC1.
70
April 27, 2007
Preliminary