LM3S610 Datasheet, PDF (44/409 Pages) List of Unclassifed Manufacturers – Microcontroller

Interrupts
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving,
which enables efficient interrupt entry. The processor supports tail-chaining, which enables
back-to-back interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 26 interrupts (listed in Table 4-2). Priorities on the
system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled
through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority
registers. You can also group priorities by splitting priority levels into pre-emption priorities and
subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type Position
Priority^a
Description
-
Reset
Non-Maskable
Interrupt (NMI)
Hard Fault
Memory
Management
Bus Fault
0
-
Stack top is loaded from first entry of vector table on
reset.
1
-3 (highest) Invoked on power up and warm reset. On first
instruction, drops to lowest priority (and then is
called the base level of activation). This is
asynchronous.
2
-2
Cannot be stopped or preempted by any exception
but reset. This is asynchronous.
An NMI is only producible by software, using the
NVIC Interrupt Control State register.
3
-1
All classes of Fault, when the fault cannot activate
due to priority or the configurable fault handler has
been disabled. This is synchronous.
4
settable MPU mismatch, including access violation and no
match. This is synchronous.
The priority of this exception can be changed.
5
settable
Pre-fetch fault, memory access fault, and other
address/memory related faults. This is synchronous
when precise and asynchronous when imprecise.
You can enable or disable this fault.
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April 27, 2007
Preliminary