LM3S610 Datasheet, PDF (217/409 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S610 Data Sheet
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to
controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked
independently.
ADC Interrupt Mask (ADCIM)
Offset 0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
MASK3 MASK2 MASK1 MASK0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
MASK3
MASK2
MASK1
MASK0
Type
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
Specifies whether the raw interrupt signal from Sample
Sequencer 3 (ADCRIS register INR3 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 2 (ADCRIS register INR2 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 1 (ADCRIS register INR1 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 0 (ADCRIS register INR0 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
April 27, 2007
217
Preliminary