NS9210B-0-I75 Datasheet, PDF (7/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

Operating frequency
Serial ports
Two fully independent serial ports (UART, SPI)
Digital phase lock loop (DPLL) for receive clock
extractions
32-byte transmit/receive FIFOs
Internal programmable bit-rate generators
Bit rates 75–230400 in 16X mode
Bit rates 1200 bps–4 Mbps in 1X mode
Flexible baud rate generator, external clock for
synchronous operation
Receive-side character and buffer gap timers
Four receive-side data match detectors
Power and Operating Voltages
500 mW maximum at 55 MHz (all outputs
switching)
418 mW maximum at 46 MHz (all outputs
switching)
291 mW maximum at 36 MHz (all outputs
switching)
3.3 V — I/O
1.5 V — Core
Bus interface
Five independent programmable chip selects
with 256 Mb addressing per chip select
Chip select support for SRAM, FP/EDO DRAM,
SDRAM, Flash, and EEPROM without external
glue
8-, 16-, and 32-bit peripheral support
External address decoding and cycle termination
Dynamic bus sizing
Internal DRAM/SDRAM controller with address
multiplexer and programmable refresh frequency
Internal refresh controller (CAS before RAS)
Burst-mode support
0–63 wait states per chip select
Address pins that configurem chip operating
modes (see "NS7520 bootstrap initialization" on
page 22)
Operating frequency
The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz,
46 MHz, and 55 MHz. The operating frequency is set during bootstrap initialization, using pins
A[8:0]. These address pins load the PLL Settings register on powerup reset. A[8:7] determines IS
(charge pump current); A[6:5] determines FS (output divider), and A[4:0] defines ND (PLL
multiplier). Each bit in A[8:0] can be set individually. See the discussion of the PLL Settings register
in the NS7520 Hardware Reference for more information.
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