NS9210B-0-I75 Datasheet, PDF (19/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

System clock and reset
System clock and reset
Symbol
Pin
XTALA1
K14
XTALA2
K12
PLLVDD (1.5V)
L15
PLLVSS
L12
RESET_
A10
I/O OD Description
I
ARM/system oscillator circuit
O
P
PLL clean power
P
PLL return
I
System reset
Signal descriptions
The NS7520 has three clock domains:
System clock (SYSCLK)
Bit rate generation and programmable timer reference clock (XTALA1/2)
System bus clock (BCLK)
The SYS module provides the NS7520 with these clocks, as well as system reset and backup
resources.
Mnemonic
XTALA1
XTALA2
PLLVDD
PLLVSS
RESET_
Signal
Description
Oscillator input
Oscillator output
A standard parallel quartz crystal or crystal oscillator can be
attached to these pins to provide the main input clock to the
NS7520.
Clean PLL power
Connect directly to the
GND plane
Power and ground for PLL circuit.
System reset
Resets the NS7520 hardware.
Table 2: Clock generation and reset signal description
This figure shows the timing and specification for RESET_ rise/fall times:
tF
tR
tF max = 18ns
Vin = 2.0Vto 0.8V
tR max = 18ns
Vin = 0.8V to 2.0V
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