NS9210B-0-I75 Datasheet, PDF (63/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

External DMA timing
External DMA timing
BCLK max frequency: 55.296 MHz
Operating conditions:
Temperature:
Voltage:
Output load:
Input drive:
-15.00 (min)
1.60 (min)
25.0pf
CMOS buffer
110.00 (max)
1.40 (max)
External DMA timing parameters
Num
72
75
70
71
73
74
Description
Min
BCLK high to DACK* valid
BCLK high to DONE* (output) valid
DREQ* low to BCLK high (setup)
5
BCLK high to DREQ* valid (hold)
0
DONE* (input) valid BCLK high (setup)
5
BLCK high to DONE* (input) valid (hold) 0
Fly-by external DMA
Max
14
15
Unit
ns
ns
ns
ns
ns
ns
T1
BCLK
Mem signals (Note-1)
DREQ*
72
DACK*
75
DONE* (output)
DONE* (input) Note2
TW
T2
71
70
72
75
74
73
Notes:
1 The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,
and PORTC3/AMUX. The timing of these signals depends on how the memory is configured
(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).
2 The DONE* signal works as an input only when the DMA channel is configured as fly-by write.
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