NS9210B-0-I75 Datasheet, PDF (55/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

FP DRAM timing
FP DRAM write
Fast Page write
T1
TW
T2
Note-1
T1
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
TA* (input)
36
BE[3:0]* ^Note-2
6
Non-muxed address
35
Muxed address
9
write D[31:0]
29
WE*
27
(FP)RAS[4:0]*
43
(FP)CAS[3:0]* ^Note-3
37
PortA2/AMUX
12
RW*
30
31
14
30
31
15
36
13
29
27
43
37
Notes:
1 If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock
pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:2]
– 32-bit port = BE[3:0]
3 Port size determines which CAS signals are active:
– 8-bit port = CAS3*
– 16-bit port = CAS[3:2]
– 32-bit port = CAS[3:0]
4 The TA* and TEA*/LAST signals are for reference only.
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