NS9210B-0-I75 Datasheet, PDF (33/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

Reset_timing
Reset_timing
From a cold start, RESET_ must be asserted until all power supplies are above their specified
thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for
crystal startup).
Due to an internal three flip-flop delay on the external RESET_ signal, after the oscillator is
settled, RESET_ must be asserted for three periods of the XTALA1 clock in these situations:
Before release of reset after application of power
While valid power is maintained to initiate hot reset (reset while power is at or above
specified thresholds)
Before loss of valid power during power outage/power down
The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the negation of
RESET_ for approximately 512 system clock cycles if the PLL is disabled. When the PLL is enabled,
PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times
the ratio of the VCO to XTALA.
VDD, VCC
1
XTALA1
2
3
4
RESET_
Reset timing parameters
Num
1
2
3
4
Description
Min Typ Max Units
Power valid before reset negated
40
ms
Note: RESET_ should remain low
for at least 40ms after power
reaches 3.0V.
Reset asserted after power valid
3
Reset asserted while power valid
3
Reset asserted before power invalid 3
T_XTALA1
T_XTALA1
T_XTALA1
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