NS9210B-0-I75 Datasheet, PDF (41/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

SRAM timing
SRAM OE burst read
OE* controlled, four word (3-2-2-2), burst read (wait = 2, BCYC = 01)
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
A[27:0]
BE[3:0]* (Note-2)
CS[4:0]*
read D[31:0]
Async OE*
CS0OE*
RW*
T1 TW T2 TW T2 TW T2 TW T2 Note-1
T1
30
30
6
36
27
11
10
28
28
18
18
12
31 31
36
27
Notes:
1 At least one null period occurs between memory transfers. More null periods can occur if the
next transfer is DMA. Thirteen clock pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:0]
– 32-bit port = BE[3:0]
3 The TW cycles are present when the WAIT field is set to 2 or more.
4 The TA* and TEA*/LAST signals are for reference only.
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