NS9210B-0-I75 Datasheet, PDF (64/68 Pages) List of Unclassifed Manufacturers – Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins

External DMA timing
Memory-to-memory external DMA
BCLK
Mem signals (Note-2)
R/W
DREQ*
DACK*
DONE* (output)
T1
TW
T2 Note-1 T1
TW
T2
71
70
71
70
72
72
72
72
75
75
75
75
Notes:
1 A null period sometimes occurs between memory cycles.
2 The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,
and PORTA2/AMUX. The timing of these signals depends on how the memory is configured
(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).
60
NS9360 Datasheet 03/2006