ISD-200 Datasheet, PDF (57/64 Pages) List of Unclassifed Manufacturers – USB Mass Storage Class Bulk-Only Specification Compliant

ISD-200 ASIC Datasheet
Appendix A – Example EEPROM or FBh Data Contents
Address
Field Name
0x00 Data Signature (LSB)
0x01 Data Signature (MSB)
0x02 Event Notification
0x03 DPLL Parameters
0x04
ATA Initialization
Timeout
0x05
Reserved – Bits [7:6]
Master/Slave Selection –
Bit [5]
Description
This field specifies the least significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
This field specifies the most significant byte of the Serial ROM/FBh
signature.
This register does not exist in HW (no POR values)
This field specifies the ATA event notification command. Setting this
field to 0x00 disables this feature.
POR configuration default of 0x00
This field denotes the parameters used by the internal DPLL. The original
clock source is 12 MHz.
5 bits M (7:3), 2 bits N (2:1), 1 bit Enable (0). When enabled, multiply the
original clock source by M, divided by N
M:
00000 => M=1
00001 => M=1
00010 => M=2
00011 => M=3
….
11111 => M=31
N:
00 => N=1
01 => N=3
10 => N=2
11 => N=4
Enable: 0 => CLK_N disabled
1 => CLK_N enabled
POR configuration default of 0x00
This field specifies the time in multiples of 128 ms (0x19 = 3.2s) before
the ISD-200 stops polling the Alternate Status device register for reset
complete and restarts the reset process.
NOTE: The ROM contents ATA Initialization Timeout value must be
large enough to accommodate I_MODE operation during the first device
initialization sequence (before FBh configuration data load)
POR configuration default of 0x02
Reserved; set to ‘0’
This bit specifies device number selection.
“0” - Drive 0
“1” - Drive 1
Example
SROM / FBh
Data
0x52
0x48
0xFC
0x43
0x02
0x01
ATAPI DEVICE RESET – This bit specifies that the ISD-200 perform a ATAPI DEVICE RESET
Bit [4]
command during a full initialization sequence.
0x06
ATA Timing – Bits [3:0]
ATA Command
Designator (Byte 0, LSB)
This field determines ATA Bus data access cycle times.
0000
reserved
0001
Mode 2 (292 ns)
0010
Mode 2 (333 ns)
0011
Mode 2 (375 ns)
0100
Mode 1 (458 ns)
0101
Mode 1 (500 ns)
0110
Mode 1 (542 ns)
0111
Mode 1 (583 ns)
1000
Mode 0 (625 ns)
1001
Mode 0 (666 ns)
1010
Mode 0 (708 ns)
1011
Mode 0 (750 ns)
1100
reserved
1101
reserved
1110
reserved
1111
reserved
POR configuration default of 0x0B
This field specifies the value in CBW CB field that designates if the CB is
decoded as ATA commands instead of the ATAPI command block.
POR configuration default of 0x00
0x24
In-System Design Confidential
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