ISD-200 Datasheet, PDF (51/64 Pages) List of Unclassifed Manufacturers – USB Mass Storage Class Bulk-Only Specification Compliant

ISD-200 ASIC Datasheet
Device Errata for First Silicon ISD-200 “0002”
This section identifies known problems with ISD-200 first silicon. Silicon revision information is obtained
from a vendor specific USB descriptor request. ISD-200 first silicon returns the English Unicode string
“0002” to the vendor specific request for string descriptor index 6. Second silicon returns “0003 for the
same string. BCDDevice from internal ROM contents also indicates revision. First silicon returns \x0100
and second silicon returns \x0110. Follow on revisions of the ISD-200 will return different descriptor
string values. Note the revision string may also be obtained by reading and decoding addresses 0x139-
0x13F from internal ROM contents.
1. CLKN output may initialize with unknown frequency with ASIC in reset
The DPLL circuitry is not asynchronously reset, and when the TEST pins are set to generate CLKN output
prior to the DPLL configuration data load, spurious frequencies may be generated from the CLKN output
prior to the state machines loading the correct DPLL m and n parameters.
This anomaly only effects I_MODE operation. Setting the TEST pins for no CLKN generation and waiting
for the configuration data load from EEPROM or on-board ROM eliminates the issue.
2. ATA_EN internal pull-up resistor is disabled during USB suspend operation
Internal logic incorrectly disables the internal pull-up resistor when the ISD-200 operates in USB suspend
mode.
The issue can be addressed with an external pull-up resistor.
3. EEPROM write operation fails on last byte of last page with some EEPROM
devices
The ISD-200 always increments the address when checking status of the previous write operation. On page
boundaries, address bits 10:8 (or the chip select portion of the address with typical 256 byte page devices)
are incremented prior to the status phase of the last byte write operation. Vendors of I2C devices that treat
this address / status phase data as “don’t care” are compatible with the ISD-200. Vendors that do examine
the address bits during the write completion check do not “ACK” the last write, as the address is now out of
range for the device.
The issue is addressed by not writing the last byte in the last EPROM page. In almost all applications only
a portion of the serial memory is utilized, and the problem does not surface. String descriptors can easily
be modified to accommodate the loss of one byte (if need be).
4. SCL output does not 3-state to hi-Z when ‘1’, limiting SCL Vhi voltage to 3.3V
This issue may cause compatibility issues for certain EEPROM devices, as most data serial ROM data
sheets report a Vhi voltage of 0.7*VCC requirement for correct operation. To operate at 400Khz (ISD-200
requirement), most devices require VCC set to 5V, which translates to a Vhi requirement of 0.7*5V=3.5V.
“Catalyst” EEPROM’s have been identified not to have the 0.7*VCC Vhi limitation. A field engineer
states Catalyst’s input stage triggers Vhi at .5*VCC, or 2.5V. Regression testing with Catalyst parts found
Zero failures. If another vendor is chosen, Vhi switching requirements must be investigated to insure
proper operation.
In-System Design Confidential
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